1. Field of the Invention
The present invention relates in general to a process for fabricating double well regions in semiconductor devices. In particular, the present invention relates to a process for fabricating double well regions in a semiconductor device that requires reduced fabrication time.
2. Technical Background
Conventional semiconductor devices having double well regions are made by growing a well region oxide layer in the designated location before a well region is formed. The formed well region is then utilized a shield layer for forming a second well region. This process characteristically requires a great deal of manufacturing time that not only increases cost but also limits the production volume.
FIGS. 1a-1f of the accompanying drawing of the present invention depict the process of fabrication of the double well-region devices in accordance with the conventional method. The drawings of FIGS. 1a-1f schematically show the cross-sectional views of the structural configuration of the semiconductor device having double well regions fabricated in accordance with the prior art techniques as selected from the process stages of its fabrication.
In the conventional process, it is well known that to fabricate a device with double well regions, a pad oxide layer 11 is first prepared on the substrate 1, as is seen in FIG. 1a. A layer of nitride 12 is then deposited to cover the pad oxide layer 11. Then, a photomask 13 is formed, shielding designated areas of the nitride layer 12, so that the exposed portions of the nitride layer 12 may be subjected to a process of etching and removal. An ion implantation process is then conducted to implant N-type impurities into areas of the substrate 1 not being shielded by both the nitride layer 2 and photomask 13. At this stage, the substrate 1 exhibits a configuration as shown in FIG. 1a.
Refer next to FIG. 1b. Utilizing the layer of nitride 12 as a shielding, an oxidation process is implemented to form a well region oxide layer 14. The nitride layer 12 is then removed.
At FIG. 1c, the well-region oxide layer 14 is now utilized as shielding for controlled implantation of P-type impurities into areas of the substrate 1 not shielded by the layer 14. A heating process then drives both the N and P impurities into the controlled depth of the substrate 1, forming the N-type well region 15 and the P-type well region 16. The well region oxide layer 14 and the pad oxide layer 11 may then be removed.
Refer next to FIG. 1d. A series of processing steps similar to those employed in the fabrication of the configuration of FIG. 1a is implemented. Namely, another pad oxide layer 17 is now grown to cover the surface of the substrate 1 at this stage, and then another nitride layer 18 is deposited thereon. Further, a photomask 19 is then formed to cover the required area of the surface which is utilized as the shielding for an etching process that removes the portions of nitride layer 18 not covered by the photomask 19. This achieves the configuration of FIG. 1d, and the photomask 19 may then be removed.
Next, in FIG. 1e, another photomask 20 is formed to cover the designated area of the configuration, so that ion implantation can be implemented to bring P-type impurities into the controlled depth of the P-type well region 16. This forms a channel stop region 21 for the subject device being fabricated. Then, the photomask 20 is removed.
Then, in FIG. 1f, the nitride layer 18 is utilized as a shielding for implementing an oxidation procedure, so that a well region oxide layer 22 may be formed on top of both the N-type well region 15 and the P-type well region 16, in the configuration as schematically shown in FIG. 1f.
The above-described process makes a double well-region device, as depicted in the drawing. However, this conventional process involves the steps for fabricating the well region oxide layer, namely the oxide layer 14 is formed in a thermal oxidation process that is necessary in the described prior art process for the formation of the P-type well region 16. Such thermal oxidation procedure is time-consuming, constituting a serious drawback to the entire device fabrication procedure. The result is increased process time that is directly translated into the increased fabrication cost, and restrained production volume.